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Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing 11
This issue of ECS Transactions includes papers presented during the 11th International Symposium on Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing held during the ECS Fall Meeting in Vienna, Austria, October 4-9, 2009.
Handbook of Applications of Chaos Theory
In addition to explaining and modeling unexplored phenomena in nature and society, chaos uses vital parts of nonlinear dynamical systems theory and established chaotic theory to open new frontiers and fields of study. Handbook of Applications of Chaos Theory covers the main parts of chaos theory along with various applications to diverse areas. Expert contributors from around the world show how chaos theory is used to model unexplored cases and stimulate new applications. Accessible to scientists, engineers, and practitioners in a variety of fields, the book discusses the intermittency route to chaos, evolutionary dynamics and deterministic chaos, and the transition to phase synchronization ...
Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing 10
This issue covers topics related to the removal of contaminants from and conditioning of Si (SOI), SiC, Ge, SiGe, and III-V semiconductor surfaces; cleaning media, including non-aqueous cleaning methods and tools; front- and back-end cleaning operations; integrated cleaning; cleaning of MEMS; photomasks (reticles); porous low-k dielectrics; post-CMP cleaning; wafer bevel cleaning and polishing; characterization, evaluation, and monitoring of cleaning; correlation with device performance as well as cleaning of equipment and storage and handling hardware. The hardcover edition includes a bonus CD-ROM of Cleaning Technology in Semiconductor Device Manufacturing 1989?2007: Proceedings from the ECS Semiconductor Cleaning Symposia 1?10. This bonus material is not available with the PDF edition.
Materials, Technology and Reliability for Advanced Interconnects and Low-K Dielectrics - 2004
The scaling of device dimensions with a simultaneous increase in functional density has imposed tremendous challenges for materials, technology, integration and reliability of interconnects. To meet requirements of the ITRS roadmap, new materials are being introduced at a faster pace in all functions of multilevel interconnects. The issues addressed in this book cannot be dispelled as simply selecting a low-k material and integrating it into a copper damascene process. The intricacies of the back end for sub-100nm technology include novel processing of low-k materials, employing pore-sealing techniques and capping layers, introducing advanced dielectric and diffusion barriers, and developing novel integration schemes. This is in addition to concerns of performance, yield, and reliability appropriate to nanoscaled interconnects. Although many challenges continue to impede progress along the ITRS roadmap, the contributions in this book confront them head-on. It provides a scientific understanding of the issues and stimulate new approaches to advanced multilevel interconnects.
