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Over the past few years, the demand for high speed Digital Signal Proces sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data ...
This book presents state-of-the-art cross-layer optimization techniques for energy-efficient information processing and routing in wireless sensor networks. Besides providing a survey on this important research area, three specific topics are discussed in detail ? information processing in a collocated cluster, information transport over a tree substrate, and information routing for computationally intensive applications. The book covers several important system knobs for cross-layer optimization, including voltage scaling, rate adaptation, and tunable compression. By exploring tradeoffs of energy versus latency and computation versus communication using these knobs, significant energy conservation is achieved.
This book constitutes the refereed proceedings of the 9th International Conference on High Performance Computing, HiPC 2002, held in Bangalore, India in December 2002. The 57 revised full contributed papers and 9 invited papers presented together with various keynote abstracts were carefully reviewed and selected from 145 submissions. The papers are organized in topical sections on algorithms, architecture, systems software, networks, mobile computing and databases, applications, scientific computation, embedded systems, and biocomputing.
This book constitutes the refereed proceedings of the 12th International Conference on Field-Programmable Logic and Applications, FPL 2002, held in Montpellier, France, in September 2002. The 104 revised regular papers and 27 poster papers presented together with three invited contributions were carefully reviewed and selected from 214 submissions. The papers are organized in topical sections on rapid prototyping, FPGA synthesis, custom computing engines, DSP applications, reconfigurable fabrics, dynamic reconfiguration, routing and placement, power estimation, synthesis issues, communication applications, new technologies, reconfigurable architectures, multimedia applications, FPGA-based arithmetic, reconfigurable processors, testing and fault-tolerance, crypto applications, multitasking, compilation techniques, etc.
This book constitutes the refereed proceedings of the 8th International Conference on High Performance Computing, HiPC 2001, held in Hyderabad, India, in December 2001. The 29 revised full papers presented together with 5 keynote papers and 3 invited papers were carefully reviewed and selected from 108 submissions. The papers are organized in topical sections on algorithms, applications, architecture, systems software, communications networks, and challenges in networking.
This book constitutes the refereed proceedings of the 11th International Conference on High-Performance Computing, HiPC 2004, held in Bangalore, India in December 2004. The 48 revised full papers presented were carefully reviewed and selected from 253 submissions. The papers are organized in topical sections on wireless network management, compilers and runtime systems, high performance scientific applications, peer-to-peer and storage systems, high performance processors and routers, grids and storage systems, energy-aware and high-performance networking, and distributed algorithms.
This volume contains the papers presented at the 1st IEEE International Conference on Distributed Computing in Sensor Systems (DCOSS 2005), which took place in Marina del Rey, California, from June 30 to July 1, 2005.
This book constitutes the refereed proceedings of the 10th International Conference on High-Performance Computing, HiPC 2003, held in Hyderabad, India in December 2003. The 48 revised full papers presented together with 5 keynote abstracts were carefully reviewed and selected from 164 submissions. The papers are organized in topical sections on performance issues and power-aware systems; distributed and network algorithms; routing in wireless, mobile, and cut-through networks; scientific and engineering applications; overlay networks, clusters, and grids; scheduling and software algorithms; network design and performance; grid applications and architecture support; performance analysis; scheduling and migration.
Most of the articles in this book deal with static or point-to-pointInterconnection Networks. In particular, new constructions are proposed basedon different tools from discrete mathematics. Many new records have beenestablished in the table of the maximum number of vertices of graphs withmaximum degree &Dgr; and diameter D. Properties of thesenetworks (and of more classical ones) are analyzed in many of the otherpapers. About 40% of the articles deal with fault tolerance orvulnerability properties using either combinatorial tools or probabilisticones.