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VLSI Design and Test
This book constitutes the refereed proceedings of the 17th International Symposium on VLSI Design and Test, VDAT 2013, held in Jaipur, India, in July 2013. The 44 papers presented were carefully reviewed and selected from 162 submissions. The papers discuss the frontiers of design and test of VLSI components, circuits and systems. They are organized in topical sections on VLSI design, testing and verification, embedded systems, emerging technology.
Designing Network On-Chip Architectures in the Nanoscale Era
Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the
Parallel and Distributed Processing and Applications
Welcome to the proceedings of ISPA 2005 which was held in the city of Nanjing. Parallel computing has become a mainstream research area in computer science and the ISPA conference has become one of the premier forums for the presentation of new and exciting research on all aspects of parallel computing. We are pleased to present the proceedings for the 3rd International Symposium on Parallel and Distributed Processing and Applications (ISPA 2005), which comprises a collection of excellent technical papers, and keynote speeches. The papers accepted cover a wide range of exciting topics, including architectures, software, networking, and applications. The conference continues to grow and this year a record total of 968 manuscripts (including workshop submissions) were submitted for consideration by the Program Committee or workshops. From the 645 papers submitted to the main conference, the Program Committee selected only 90 long papers and 19 short papers in the program. Eight workshops complemented the outstanding paper sessions.
High Performance Computing
I wish to welcome all of you to the International Symposium on High Perf- mance Computing 2000 (ISHPC 2000) in the megalopolis of Tokyo. After having two great successes with ISHPC’97 (Fukuoka, November 1997) and ISHPC’99 (Kyoto, May 1999), many people have requested that the symposium would be held in the capital of Japan and we have agreed. I am very pleased to serve as Conference Chair at a time when high p- formance computing (HPC) has a signi?cant in?uence on computer science and technology. In particular, HPC has had and will continue to have a signi?cant - pact on the advanced technologies of the “IT” revolution. The many conferences and symposiums that are held on the subject around the world are an indication of the importance of this area and the interest of the research community. One of the goals of this symposium is to provide a forum for the discussion of all aspects of HPC (from system architecture to real applications) in a more informal and personal fashion. Today we are delighted to have this symposium, which includes excellent invited talks, tutorials and workshops, as well as high quality technical papers.
Euro-Par 2012 Parallel Processing
This book constitutes the thoroughly refereed proceedings of the 18th International Conference, Euro-Par 2012, held in Rhodes Islands, Greece, in August 2012. The 75 revised full papers presented were carefully reviewed and selected from 228 submissions. The papers are organized in topical sections on support tools and environments; performance prediction and evaluation; scheduling and load balancing; high-performance architectures and compilers; parallel and distributed data management; grid, cluster and cloud computing; peer to peer computing; distributed systems and algorithms; parallel and distributed programming; parallel numerical algorithms; multicore and manycore programming; theory and algorithms for parallel computation; high performance network and communication; mobile and ubiquitous computing; high performance and scientific applications; GPU and accelerators computing.
Embedded Computer Systems: Architectures, Modeling, and Simulation
This book constitutes the refereed proceedings of the 20th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2020, held in Samos, Greece, in July 2020.* The 16 regular papers presented were carefully reviewed and selected from 35 submissions. In addition, 9 papers from two special sessions were included, which were organized on topics of current interest: innovative architectures for security and European projects on embedded and high performance computing for health applications. * The conference was held virtually due to the COVID-19 pandemic.
High Performance Computing - HiPC 2007
This book constitutes the refereed proceedings of the 14th International Conference on High-Performance Computing, HiPC 2007, held in Goa, India, in December 2007. The 53 revised full papers presented together with the abstracts of five keynote talks were carefully reviewed and selected from 253 submissions. The papers are organized in topical sections on a broad range of applications including I/O and FPGAs, and microarchitecture and multiprocessor architecture.
Scientific Computing with Multicore and Accelerators
The hybrid/heterogeneous nature of future microprocessors and large high-performance computing systems will result in a reliance on two major types of components: multicore/manycore central processing units and special purpose hardware/massively parallel accelerators. While these technologies have numerous benefits, they also pose substantial perfo
Parallel Computing is Everywhere
The most powerful computers work by harnessing the combined computational power of millions of processors, and exploiting the full potential of such large-scale systems is something which becomes more difficult with each succeeding generation of parallel computers. Alternative architectures and computer paradigms are increasingly being investigated in an attempt to address these difficulties. Added to this, the pervasive presence of heterogeneous and parallel devices in consumer products such as mobile phones, tablets, personal computers and servers also demands efficient programming environments and applications aimed at small-scale parallel systems as opposed to large-scale supercomputers....
Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design
With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-pu...
