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Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits
"The last couple of years have been very busy for the semiconductor industry and researchers. The rapid speed of production channel length reduction has brought lithographic challenges to semiconductor modeling. These include stress optimization, transisto"
VLSI-SoC: Internet of Things Foundations
This book contains extended and revised versions of the best papers presented at the 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, held in Playa del Carmen, Mexico, in October 2014. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.
Quantum Computing in Cybersecurity
Machine learning, deep learning, probabilistic neural networks, blockchain, and other new technologies all demand extremely high processing speeds. A quantum computer is an example of such a system. Quantum computers may be accessed over the internet. This technology poses a significant risk, since quantum terrorists, or cyber criminals, coul be able to cause many problems, including bringing down the internet. The principles of quantum mechanics might be used by evil doers to destroy quantum information on a global scale, and an entire class of suspicious codes could destroy data or eavesdrop on communication. Quantum physics, however, safeguards against data eavesdropping. A significant am...
Characterization, Modeling and Optimization of Fills and Stress in Semiconductor Integrated Circuits
To improve manufacturability and yield, a number of fill structures are used in semiconductor manufacturing. These structures are CMP, active region (diffusion) and via fills. CMP (dummy) fills are used to reduce metal thickness variations due to chemical-mechanical polishing (CMP). Via fills are used to improve neighboring via printability, to improve mechanical stability of low-k dielectrics, and to reduce via resistance variability. Active region fills are used for STI CMP uniformity and threshold voltage variation reduction. Contact fills may be used for contact printability enhancement and contact resistance variability reduction. In this thesis, we additionally utilize via fills for re...
Inside Health Care
"Health care in the US is facing a crisis, but there is polarization and disagreement among policy makers and the public about how to solve this crisis. The overall outcome is ranked much lower than most developed nations and nearly 50 million people are u"
Handbook of Algorithms for Physical Design Automation
The physical design flow of any project depends upon the size of the design, the technology, the number of designers, the clock frequency, and the time to do the design. As technology advances and design-styles change, physical design flows are constantly reinvented as traditional phases are removed and new ones are added to accommodate changes in technology. Handbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitio...
Low-Power Variation-Tolerant Design in Nanometer Silicon
Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.
More than Moore Technologies for Next Generation Computer Design
This book provides a comprehensive overview of key technologies being used to address challenges raised by continued device scaling and the extending gap between memory and central processing unit performance. Authors discuss in detail what are known commonly as “More than Moore” (MtM), technologies, which add value to devices by incorporating functionalities that do not necessarily scale according to “Moore's Law”. Coverage focuses on three key technologies needed for efficient power management and cost per performance: novel memories, 3D integration and photonic on-chip interconnect.
