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Delay Fault Testing for VLSI Circuits
In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of t...
Embedded Software and Systems
Welcome to the proceedings of the 2005 International Conference on Emb- ded Software and Systems (ICESS 2005) held in Xian, China, December 16-18, 2005. With the advent of VLSI system level integration and system-on-chip, the center of gravity of the computer industry is now moving from personal c- puting into embedded computing. Embedded software and systems are incre- ingly becoming a key technological component of all kinds of complex technical systems, ranging from vehicles, telephones, aircraft, toys, security systems, to medical diagnostics, weapons, pacemakers, climate control systems, etc. The ICESS 2005 conference provided a premier international forum for - searchers, developers and providers from academia and industry to address all resulting profound challenges; to present and discuss their new ideas, - search results, applications and experience; to improve international com- nication and cooperation; and to promote embedded software and system - dustrialization and wide applications on all aspects of embedded software and systems.
Engineering of Intelligent Systems
This book constitutes the refereed proceedings of the 14th International Conference on Industrial and Engineering Applications of Artificial Intelligence and Export Systems, IEA/AIE 2001, held in Budapest, Hungary in June 2001. The 104 papers presented were carefully reviewed and selected from a total of 140 submissions. The proceedings offer topical sections on searching, knowledge representation, model-based reasoning, machine learning, data mining, soft computing, evolutionary algorithms, distributed problem solving, export systems, pattern and speech recognition, vision language processing, planning and scheduling, robotics, autonomous agents, design, control, manufacturing systems, finance and business, software engineering, and intelligent tutoring.
Emerging Nanotechnologies
Emerging Nanotechnologies: Test, Defect Tolerance and Reliability covers various technologies that have been developing over the last decades such as chemically assembled electronic nanotechnology, Quantum-dot Cellular Automata (QCA), and nanowires and carbon nanotubes. Each of these technologies offers various advantages and disadvantages. Some suffer from high power, some work in very low temperatures and some others need indeterministic bottom-up assembly. These emerging technologies are not considered as a direct replacement for CMOS technology and may require a completely new architecture to achieve their functionality. Emerging Nanotechnologies: Test, Defect Tolerance and Reliability brings all of these issues together in one place for readers and researchers who are interested in this rapidly changing field.
Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design
With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-pu...
18th IEEE VLSI Test Symposium
Proceedings of a spring 2000 symposium, highlighting novel ideas and approaches to current and future problems related to testing of electronic circuits and systems. Themes are microprocessor test/validation, low power BIST and scan, technology trends, scan- related approaches, defect-driven techniques, and system-on-chip test techniques. Other subjects are analog test techniques, temperature and process drift issues, test compaction and design validation, analog BIST, and functional test and verification issues. Also covered are STIL extension, IDDQ test, and on-line testing and fault tolerance. Lacks a subject index. Annotation copyrighted by Book News, Inc., Portland, OR.
