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This book constitutes revised selected papers from the 10th International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2019, held in Darmstadt, Germany, in April 2019. The 14 papers presented together with one keynote and one invited talk in this volume were carefully reviewed and selected from 34 submissions. They were organized in topical sections named: Side-Channel Attacks; Fault-Injection Attacks; White-Box Attacks; Side-Channel Analysis Methodologies; Security Aspects of Post-Quantum Schemes; and Countermeasures Against Implementation Attacks.
Circuits and Systems for Security and Privacy begins by introducing the basic theoretical concepts and arithmetic used in algorithms for security and cryptography, and by reviewing the fundamental building blocks of cryptographic systems. It then analyzes the advantages and disadvantages of real-world implementations that not only optimize power, area, and throughput but also resist side-channel attacks. Merging the perspectives of experts from industry and academia, the book provides valuable insight and necessary background for the design of security-aware circuits and systems as well as efficient accelerators used in security applications.
This book constitutes the refereed proceedings of the 11th International Workshop on Security, IWSEC 2016, held in Tokyo, Japan, in September 2016. The 15 regular papers and 4 short papers presented in this volume were carefully reviewed and selected from 53 submissions. They were organized in topical sections named: system security; searchable encryption; cryptanalysis; permutation and symmetric encryption; privacy preserving; hardware security; post-quantum cryptography; and paring computation.
Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems. Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems.
Alexander Biedermann presents a generic hardware-based virtualization approach, which may transform an array of any off-the-shelf embedded processors into a multi-processor system with high execution dynamism. Based on this approach, he highlights concepts for the design of energy aware systems, self-healing systems as well as parallelized systems. For the latter, the novel so-called Agile Processing scheme is introduced by the author, which enables a seamless transition between sequential and parallel execution schemes. The design of such virtualizable systems is further aided by introduction of a dedicated design framework, which integrates into existing, commercial workflows. As a result, this book provides comprehensive design flows for the design of embedded multi-processor systems-on-chip.
This book constitutes revised selected papers from the 11th International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2020, held in Lugano, Switzerland, in April 2020. Due to COVID-19, the workshop was held online. The 15 papers presented in this volume were carefully reviewed and selected from 36 submissions. The workshop covers subjects from wide ranges such as secure design, side channel attacks and countermeasures, and architectures and protocols.
This book constitutes the refereed proceedings of the 19th International Conference on Cryptology in India, INDOCRYPT 2018, held in New Delhi, India, in December 2018. The 20 revised full papers presented in this book were carefully reviewed and selected from 60 submissions. The focus of the conference includes works on outsourced computation and searchable encryption; symmetric key cryptography and format preserving encryption; fault attacks and Hash functions; post quantum cryptography; asymmetric key cryptography and cryptanalysis; symmetric key cryptanalysis; theory; and secure computations and protocols.
This book constitutes the refereed proceedings of the Cryptographers' Track at the RSA Conference 2012, CT-RSA 2012, held in San Francisco, CA, USA, in February/March 2012. The 26 revised full papers presented were carefully reviewed and selected from 113 submissions. The papers are organized in topical sections on side channel attacks, digital signatures, public-key encryption, cryptographic protocols, secure implementation methods, symmetric key primitives, and secure multiparty computation.
This book constitutes revised selected papers from the 13th International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2022, held in Leuven, Belgium, in April 2022. The 12 full papers presented in this volume were carefully reviewed and selected from 25 submissions. The papers cover the following subjects: implementation attacks, secure implementation, implementation attack-resilient architectures and schemes, secure design and evaluation, practical attacks, test platforms, and open benchmarks.
This book describes the current state of the art in big-data analytics, from a technology and hardware architecture perspective. The presentation is designed to be accessible to a broad audience, with general knowledge of hardware design and some interest in big-data analytics. Coverage includes emerging technology and devices for data-analytics, circuit design for data-analytics, and architecture and algorithms to support data-analytics. Readers will benefit from the realistic context used by the authors, which demonstrates what works, what doesn’t work, and what are the fundamental problems, solutions, upcoming challenges and opportunities. Provides a single-source reference to hardware architectures for big-data analytics; Covers various levels of big-data analytics hardware design abstraction and flow, from device, to circuits and systems; Demonstrates how non-volatile memory (NVM) based hardware platforms can be a viable solution to existing challenges in hardware architecture for big-data analytics.