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Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission
This book explains concepts behind fractional subsampling-based frequency synthesis that is re-shaping today’s art in the field of low-noise LO generation. It covers advanced material, giving clear guidance for development of background-calibrated environments capable of spur-free synthesis and wideband phase modulation. It further expands the concepts into the field of subsampling polar transmission, where the newly developed architecture enables unprecedented spectral efficiency levels, unquestionably required by the upcoming generation of wireless standards.
Phase-Locked Frequency Generation and Clocking
Phase-Locked Frequency Generation and Clocking covers essential topics and issues in current Phase-Locked Loop design, from a light touch of fundamentals to practical design aspects. Both wireless and wireline systems are considered in the design of low noise frequency generation and clocking systems. Topics covered include architecture and design, digital-intensive Phase-Locked Loops, low noise frequency generation and modulation, clock-and-data recovery, and advanced clocking and clock generation systems.
Understanding Delta-Sigma Data Converters
This new edition introduces operation and design techniques for Sigma-Delta converters in physical and conceptual terms, and includes chapters which explore developments in the field over the last decade Includes information on MASH architectures, digital-to-analog converter (DAC) mismatch and mismatch shaping Investigates new topics including continuous-time ΔΣ analog-to-digital converters (ADCs) principles and designs, circuit design for both continuous-time and discrete-time ΔΣ ADCs, decimation and interpolation filters, and incremental ADCs Provides emphasis on practical design issues for industry professionals
Quadrature RC−Oscillators
This book presents a tutorial review of van der Pol model, a universal oscillator model for the analysis of modern RC−oscillators in weak and strong nonlinear regimes. A detailed analysis of the injection locking in van der Pol oscillators is also presented. The relation between the van der Pol parameters and several circuit implementations in CMOS nanotechnology is given, showing that this theory is very useful in the optimization of oscillator key parameters, such as: frequency, amplitude and phase relationship. The authors discuss three different examples: active coupling RC−oscillators, capacitive coupling RC−oscillators, and two-integrator oscillator working in the sinusoidal regi...
Memristor Technology: Synthesis and Modeling for Sensing and Security Applications
This book provides readers with a single-source guide to fabricate, characterize and model memristor devices for sensing applications. The authors describe a correlated, physics-based model to simulate and predict the behavior of devices fabricated with different oxide materials, active layer thickness, and operating temperature. They discuss memristors from various perspectives, including working mechanisms, different synthesis methods, characterization procedures, and device employment in radiation sensing and security applications.
CMOS Integrated Circuit Design for Wireless Power Transfer
This book presents state-of-the-art analog and power management IC design techniques for various wireless power transfer (WPT) systems. To create elaborate power management solutions, circuit designers require an in-depth understanding of the characteristics of each converter and regulator in the power chain. This book addresses WPT design issues at both system- and circuit-level, and serves as a handbook offering design insights for research students and engineers in the integrated power electronics area.
Energy-Efficient Smart Temperature Sensors in CMOS Technology
This book describes the design and implementation of energy-efficient smart (digital output) temperature sensors in CMOS technology. To accomplish this, a new readout topology, namely the zoom-ADC, is presented. It combines a coarse SAR-ADC with a fine Sigma-Delta (SD) ADC. The digital result obtained from the coarse ADC is used to set the reference levels of the SD-ADC, thereby zooming its full-scale range into a small region around the input signal. This technique considerably reduces the SD-ADC’s full-scale range, and notably relaxes the number of clock cycles needed for a given resolution, as well as the DC-gain and swing of the loop-filter. Both conversion time and power-efficiency ca...
