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The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits
IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier without too much penalty regarding area while keeping the gain-bandwidth unaffected in the same time? Moderate inversion yields high gains, but the concomitant area increase adds parasitics that restrict bandwidth. Which methodology to use in order to come across the best compromise(s)? Is synthesis a mixture of design experience combined with cut and tries or is it a constrained multivariate opt...
Neurocomputing
This volume contains the collected papers of the NATO Conference on Neurocomputing, held in Les Arcs in February 1989. For many of us, this conference was reminiscent of another NATO Conference, in 1985, on Disordered Systems [1], which was the first conference on neural nets to be held in France. To some of the participants that conference opened, in a way, the field of neurocomputing (somewhat exotic at that time!) and also allowed for many future fruitful contacts. Since then, the field of neurocomputing has very much evolved and its audience has increased so widely that meetings in the US have often gathered more than 2000 participants. However, the NATO workshops have a distinct atmosphere of free discussions and time for exchange, and so, in 1988, we decided to go for another session. This was an ~casion for me and some of the early birds of the 1985 conference to realize how much, and how little too, the field had matured.
SOC Design Methodologies
The 11 th IFIP International Conference on Very Large Scale Integration, in Montpellier, France, December 3-5,2001, was a great success. The main focus was about IP Cores, Circuits and System Designs & Applications as well as SOC Design Methods and CAD. This book contains the best papers (39 among 70) that have been presented during the conference. Those papers deal with all aspects of importance for the design of the current and future integrated systems. System on Chip (SOC) design is today a big challenge for designers, as a SOC may contain very different blocks, such as microcontrollers, DSPs, memories including embedded DRAM, analog, FPGA, RF front-ends for wireless communications and i...
Low Power Analog CMOS for Cardiac Pacemakers
Low Power Analog CMOS for Cardiac Pacemakers proposes new techniques for the reduction of power consumption in analog integrated circuits. Our main example is the pacemaker sense channel, which is representative of a broader class of biomedical circuits aimed at qualitatively detecting biological signals. The first and second chapters are a tutorial presentation on implantable medical devices and pacemakers from the circuit designer point of view. This is illustrated by the requirements and solutions applied in our implementation of an industrial IC for pacemakers. There from, the book discusses the means for reduction of power consumption at three levels: base technology, power-oriented analytical synthesis procedures and circuit architecture.
Applied Parallel Computing: Advanced Scientific Computing
This book constitutes the refereed proceedings of the 6th International Conference on Applied Parallel Computing, PARA 2002, held in Espoo, Finland, in June 2002. The 50 revised full papers presented together with nine keynote lectures were carefully reviewed and selected for inclusion in the proceedings. The papers are organized in topical sections on data mining and knowledge discovery, parallel program development, practical experience in parallel computing, computer science, numerical algorithms with hierarchical memory optimization, numerical methods and algorithms, cluster computing, grid and network technologies, and physics and applications.
Proceedings
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Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has...
VLSI: Integrated Systems on Silicon
This book contains the papers that have been presented at the ninth Very Large Scale Integrated Systems conference VLSI'97 that is organized biannually by IFIP Working Group 10.5. It took place at Hotel Serra Azul, in Gramado Brazil from 26-30 August 1997. Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble and Tokyo. The papers in this book report on all aspects of importance to the design of the current and future integrated systems. The current trend towards the realization of versatile Systems-on-a-Chip require attention of embedded hardware/software systems, dedicated ASIC hardware, sensors and actuators, mixed analog/digital design, video and imag...
Cinema 16
The history of Cinema 16--the nation's first film society--through letters, programs, interviews, and the society's own documents.
